This invention relates generally to a synchronizer circuit for synchronizing an asynchronous input signal to an internal clock signal, and more particularly, to a two stage CMOS synchronizer circuit having matched switch (threshold) points.
In order to optimize speed and performance, it is often necessary to operate different portions of a digital processing system at different clock frequencies. This requires that certain portions of the system be capable of receiving and processing signals which are asynchronous with respect to a local clock signal. To avoid meta-stable states (intermediate voltage levels due to the sampling of asynchronous inputs without a guaranteed set up time) and to generate full voltage swing control signals, synchronizer circuits are employed to receive the asynchronous input signal and synchronize it with the local clock signal.
A synchronizer circuit may include first and second stages of differential sense amplifiers separated by buffer circuitry. Unfortunately, if the switch point of the buffer circuitry does not match that of the first stage sense amplifier and if the output differential voltage of the first stage sense amplifier is very small (e.g. 200 millivolts), the input to the second stage sense amplifier may not be sufficiently amplified by the buffer circuitry. This occurs since the gain of the buffer circuitry is highest at its switch point which may not necessarily coincide with that of the first stage sense amplifier. The problem is further aggravated if the second stage sense amplifier has a switch point which is not matched to that of the first stage sense amplifier and buffer circuitry. It is therefore necessary to provide a synchronizer circuit which is characterized by matched switch points.